How electricity flows from the utility grid down to a chip
Every watt a chip consumes starts as high-voltage AC at a power plant hundreds of miles away. In a traditional 415 V AC hall, that feed is stepped down, conditioned by a double-conversion UPS, and rectified in the rack to a 54 V or 12 V bus. A point-of-load regulator then makes the sub-1 V core rail the chip actually uses. The diagram counts that path as seven stages, including transmission and the hall busway, which are not conversions. NVIDIA's 800 V DC architecture, targeted at 1 MW racks from 2027, collapses the low-voltage transformer, the AC UPS, and the rack AC→DC stage into one medium-voltage rectifier. 1500 V DC sits at the usual top of the low-voltage class (IEC 62477-1 stops at 1500 V DC; the NEC treats anything above 1500 V DC as high voltage) and is already common in utility-scale solar and rail. NVIDIA's white paper lists it as a potential later target, and OCP's LVDC work discusses it as a progression. It is not required to reach multi-megawatt racks — NVIDIA's 800 V DC design is meant to scale past 1 MW.
End-to-end percentages are the product of the stage efficiencies in that path. The 1500 V stage efficiencies are illustrative; NVIDIA and OCP have not published a measured chain efficiency for that path. The copper figures are separate: NVIDIA reports about 45% less copper from 415 V AC to 800 V DC, and its cable comparison shows about 45% less copper for 1500 V DC than for 800 V DC at the same power (3.1 versus 1.7 kW/mm²).